m255
K3
13
cModel Technology
Z0 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Filters\Single MAC FIR Filters\MAC FIR 16-tap\MAC_FIR\simulation
Ecoef_ram
Z1 w1381412596
Z2 DPx3 std 6 textio 0 22 5>J:;AW>W0[[dW0I6EN1Q0
Z3 DPx4 ieee 14 std_logic_1164 0 22 5=aWaoGZSMWIcH0i^f`XF1
Z4 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Filters\Single MAC FIR Filters\MAC FIR 16-tap\MAC_FIR\simulation
Z5 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Single MAC FIR Filters/MAC FIR 16-tap/MAC_FIR/synthesis/MAC_FIR.vhd
Z6 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Single MAC FIR Filters/MAC FIR 16-tap/MAC_FIR/synthesis/MAC_FIR.vhd
l0
L734
V43a?U@`A@:fI0>EX4IoAY0
Z7 OW;C;10.1c;51
31
Z8 !s108 1382078144.676000
Z9 !s90 -reportprogress|300|-93|-explicit|-work|postsynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Single MAC FIR Filters/MAC FIR 16-tap/MAC_FIR/synthesis/MAC_FIR.vhd|
Z10 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Single MAC FIR Filters/MAC FIR 16-tap/MAC_FIR/synthesis/MAC_FIR.vhd|
Z11 o-93 -explicit -work postsynth -O0
!s100 Ch5FC@;9IoN`XcZ6m>JdQ2
!i10b 1
Adef_arch
Z12 DEx4 work 24 coef_ram_coef_ram_0_uram 0 22 X5@e04MP^oLk7hO^8L9]40
R2
R3
Z13 DEx4 work 8 coef_ram 0 22 43a?U@`A@:fI0>EX4IoAY0
l768
L744
Va6TnOS1mJ1WJKQce5ESzV1
!s100 ?cG8AJ@]27UW20BhiFbEJ2
R7
31
R8
R9
R10
R11
!i10b 1
Ecoef_ram_coef_ram_0_uram
R1
R2
R3
R4
R5
R6
l0
L583
VX5@e04MP^oLk7hO^8L9]40
R7
31
R8
R9
R10
R11
!s100 OKWQnzYKHTdD:SgenN98`1
!i10b 1
Adef_arch
R2
R3
R12
l654
L593
VQV?N9><cE>L:lFXL5goEX3
!s100 6IbhOMUzbD[MAc3WoAchn2
R7
31
R8
R9
R10
R11
!i10b 1
Einp_ram
R1
R2
R3
R4
R5
R6
l0
L164
VRQgHPEdnY8Y1^]7Re8:6;0
R7
31
R8
R9
R10
R11
!s100 9E3:RHBTjf2nPkY7L6LHm1
!i10b 1
Adef_arch
Z14 DEx4 work 22 inp_ram_inp_ram_0_uram 0 22 oFHTJ4Qjn>5F<7gKmnYWJ2
R2
R3
Z15 DEx4 work 7 inp_ram 0 22 RQgHPEdnY8Y1^]7Re8:6;0
l204
L177
VI7oOjmD1YIS=DgE;^lnRn2
!s100 Y;b@c>Ef5[dECW?;__LA?2
R7
31
R8
R9
R10
R11
!i10b 1
Einp_ram_inp_ram_0_uram
R1
R2
R3
R4
R5
R6
l0
L8
VoFHTJ4Qjn>5F<7gKmnYWJ2
R7
31
R8
R9
R10
R11
!s100 LJhfF4G4:VWk?GR?9^0`J0
!i10b 1
Adef_arch
R2
R3
R14
l82
L21
V``beKZY59i51ML95NbVKj2
!s100 XneWc0UifP?JL]RzWYZLO3
R7
31
R8
R9
R10
R11
!i10b 1
Emac_fir
R1
R2
R3
R4
R5
R6
l0
L803
V4INRa_1mTP6SfCOmzbF=m3
R7
31
R8
R9
R10
R11
!s100 JUW=1hBX;]e?[^55lf6:T3
!i10b 1
Adef_arch
R13
Z16 DEx4 work 12 mulacc_18x18 0 22 PDlY>_DNYBbRaDQDG;]5h3
R15
R2
R3
DEx4 work 7 mac_fir 0 22 4INRa_1mTP6SfCOmzbF=m3
l1026
L816
Vomg5Q5]=3Mn9n=j9lL:]22
!s100 >S1m:21zHgGCXA2bI]?CE2
R7
31
R8
R9
R10
R11
!i10b 1
Emulacc_18x18
R1
R2
R3
R4
R5
R6
l0
L481
VPDlY>_DNYBbRaDQDG;]5h3
R7
31
R8
R9
R10
R11
!s100 <Qc0DHk?NUXnee3QozPjz1
!i10b 1
Adef_arch
Z17 DEx4 work 41 mulacc_18x18_mulacc_18x18_0_hard_mult_acc 0 22 7Ndd[cMPz_M3Tf1QANi;;3
R2
R3
R16
l518
L492
V1a5a6?XQ8<=>ZVRb<WW=03
!s100 YQe9JkC36iZR8XVS_YeGZ1
R7
31
R8
R9
R10
R11
!i10b 1
Emulacc_18x18_mulacc_18x18_0_hard_mult_acc
R1
R2
R3
R4
R5
R6
l0
L256
V7Ndd[cMPz_M3Tf1QANi;;3
R7
31
R8
R9
R10
R11
!s100 ;]Q95NfNhGF0@[OWLnm<H2
!i10b 1
Adef_arch
R2
R3
R17
l347
L268
V8mH@bdilMcX3XiiIHD]PB3
!s100 DIPb:B6gId8j8db6YdZ5n0
R7
31
R8
R9
R10
R11
!i10b 1
Etestbench_macfir
Z18 w1381993606
Z19 DPx4 ieee 15 std_logic_arith 0 22 4`Y?g_lkdn;7UL9IiJck01
Z20 DPx4 ieee 16 std_logic_signed 0 22 E>OLoMaBGQ?hbGgOoNXM^1
R2
R3
R4
Z21 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Single MAC FIR Filters/MAC FIR 16-tap/MAC_FIR/stimulus/MAC_FIR_Testbench.vhd
Z22 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Single MAC FIR Filters/MAC FIR 16-tap/MAC_FIR/stimulus/MAC_FIR_Testbench.vhd
l0
L21
V0Ee=9nRQFESSd9f`=8BOl3
!s100 TDFnZM<GYfQ@fA<RSH;Dm3
R7
31
!i10b 1
Z23 !s108 1382078148.373000
Z24 !s90 -reportprogress|300|-93|-explicit|-work|postsynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Single MAC FIR Filters/MAC FIR 16-tap/MAC_FIR/stimulus/MAC_FIR_Testbench.vhd|
Z25 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Single MAC FIR Filters/MAC FIR 16-tap/MAC_FIR/stimulus/MAC_FIR_Testbench.vhd|
R11
Amacfir_testbench_arch
R19
R20
R2
R3
Z26 DEx4 work 16 testbench_macfir 0 22 0Ee=9nRQFESSd9f`=8BOl3
l49
L24
Vf8@D=OFXDYO5ZkDl:CnfP1
!s100 e8XF7cX5nMfL^;8L:@J];3
R7
31
!i10b 1
R23
R24
R25
R11
